`ifndef UDLY
`define UDLY 1
`endif
module mem_mux__11(
  mem_req__0__valid,
  mem_req__0__ready,
  mem_req__0__we_n,
  mem_req__0__addr,
  mem_req__0__rdata,
  mem_req__0__wdata,
  mem__0__ce_n,
  mem__0__we_n,
  mem__0__addr,
  mem__0__rdata,
  mem__0__wdata,
  mem__1__ce_n,
  mem__1__we_n,
  mem__1__addr,
  mem__1__rdata,
  mem__1__wdata,
  clk,
  rstn
);
//parameter declare
//port declare
input mem_req__0__valid;
output mem_req__0__ready;
input mem_req__0__we_n;
input [31:0] mem_req__0__addr;
output [63:0] mem_req__0__rdata;
input [63:0] mem_req__0__wdata;
output mem__0__ce_n;
output mem__0__we_n;
output [31:0] mem__0__addr;
input [63:0] mem__0__rdata;
output [63:0] mem__0__wdata;
output mem__1__ce_n;
output mem__1__we_n;
output [31:0] mem__1__addr;
input [63:0] mem__1__rdata;
output [63:0] mem__1__wdata;
input clk;
input rstn;
//channel declare
//wire declare
logic __mem_sel_1037;
logic __mem_sel_1038;
logic [1:0] __mem_sel_idx_1039;
logic __mem_sel_1041;
logic __mem_sel_1042;
logic [1:0] __mem_sel_idx_1043;
logic __mux2req_ready_1046;
logic __t_1047;
logic __t_1048;
logic __ret_1050;
logic __index_1051;
logic __index_1052;
logic __valid_1053;
logic __cond_1054;
logic __cond_1055;
logic __valid_1056;
logic __cond_1057;
logic __cond_1058;
logic __ret_1060;
logic __index_1061;
logic __index_1062;
logic __valid_1063;
logic __cond_1064;
logic __cond_1065;
logic __valid_1066;
logic __cond_1067;
logic __cond_1068;
logic __cond_1069;
logic __cond_1070;
logic [31:0] __addr_t_1071;
logic __cond_1072;
logic [31:0] __mem_addr_t_1073;
logic __cond_1074;
logic __cond_1075;
logic [31:0] __addr_t_1076;
logic __cond_1077;
logic [31:0] __mem_addr_t_1078;
logic __cond_1079;
logic __cond_1080;
//port wire declare
wire mem_req__0__valid;
logic mem_req__0__ready;
wire mem_req__0__we_n;
wire [31:0] mem_req__0__addr;
logic [63:0] mem_req__0__rdata;
wire [63:0] mem_req__0__wdata;
logic mem__0__ce_n;
logic mem__0__we_n;
logic [31:0] mem__0__addr;
wire [63:0] mem__0__rdata;
logic [63:0] mem__0__wdata;
logic mem__1__ce_n;
logic mem__1__we_n;
logic [31:0] mem__1__addr;
wire [63:0] mem__1__rdata;
logic [63:0] mem__1__wdata;
wire clk;
wire rstn;
//register declare
//register init and update
reg [1:0] __mem_sel_idx_dly_1040;
wire [1:0] ___mem_sel_idx_dly_1040;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mem_sel_idx_dly_1040 <= #`UDLY 2'h0;
  end
  else begin
    __mem_sel_idx_dly_1040 <= #`UDLY ___mem_sel_idx_dly_1040;
  end
end

reg [1:0] __mem_sel_idx_dly_1044;
wire [1:0] ___mem_sel_idx_dly_1044;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mem_sel_idx_dly_1044 <= #`UDLY 2'h0;
  end
  else begin
    __mem_sel_idx_dly_1044 <= #`UDLY ___mem_sel_idx_dly_1044;
  end
end

reg __mux2req_ready_dly_1045;
wire ___mux2req_ready_dly_1045;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mux2req_ready_dly_1045 <= #`UDLY 1'h0;
  end
  else begin
    __mux2req_ready_dly_1045 <= #`UDLY ___mux2req_ready_dly_1045;
  end
end

reg __round_1049;
wire ___round_1049;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __round_1049 <= #`UDLY 1'h0;
  end
  else begin
    __round_1049 <= #`UDLY ___round_1049;
  end
end

reg __round_1059;
wire ___round_1059;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __round_1059 <= #`UDLY 1'h0;
  end
  else begin
    __round_1059 <= #`UDLY ___round_1059;
  end
end

//assign logic
assign __t_1047 /* 64 */ = ((0<=mem_req__0__addr)&&(mem_req__0__addr<511) /* 434 */ ) /* 64 */ ;
assign __mem_sel_1037 /* 65 */ = (__t_1047 /* 66 */ )?(mem_req__0__valid /* 67 */ ):1'b0 /* 69 */  /* 68 */ ;
assign __t_1048 /* 64 */ = ((512<=mem_req__0__addr)&&(mem_req__0__addr<1023) /* 434 */ ) /* 64 */ ;
assign __mem_sel_1041 /* 65 */ = (__t_1048 /* 66 */ )?(mem_req__0__valid /* 67 */ ):1'b0 /* 69 */  /* 68 */ ;
assign ___round_1049 /* 330 */ = (1'b1 /* 331 */ )?((__ret_1050==2-1 /* 332 */ )?(0 /* 332 */ ):__ret_1050+1 /* 333 */  /* 333 */ ):__round_1049 /* 335 */  /* 334 */ ;
assign __index_1051 /* 337 */ = __round_1049 /* 337 */ ;
assign __index_1052 /* 339 */ = ((__round_1049+1)>=2 /* 340 */ )?(__round_1049+1-2 /* 341 */ ):__round_1049+1 /* 343 */  /* 342 */ ;
assign __cond_1054 /* 242 */ = 0==__index_1051 /* 242 */ ;
assign __cond_1055 /* 242 */ = 1==__index_1051 /* 242 */ ;
assign __valid_1053 /* 346 */ = ((({ 1{__cond_1054} }&((__mem_sel_1037 /* 312 */ ))) /* 244 */ )|({ 1{__cond_1055} }&((__mem_sel_1038 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_1057 /* 242 */ = 0==__index_1052 /* 242 */ ;
assign __cond_1058 /* 242 */ = 1==__index_1052 /* 242 */ ;
assign __valid_1056 /* 346 */ = ((({ 1{__cond_1057} }&((__mem_sel_1037 /* 312 */ ))) /* 244 */ )|({ 1{__cond_1058} }&((__mem_sel_1038 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __ret_1050 /* 349 */ = (__valid_1053 /* 215 */ )?(__index_1051 /* 216 */ ):(__valid_1056 /* 215 */ )?(__index_1052 /* 216 */ ):(2 /* 213 */ ) /* 218 */  /* 217 */  /* 217 */ ;
assign __mem_sel_idx_1039 /* 80 */ = (__ret_1050 /* 350 */ ) /* 80 */ ;
assign ___mem_sel_idx_dly_1040 /* 81 */ = __mem_sel_idx_1039 /* 81 */ ;
assign ___round_1059 /* 330 */ = (1'b1 /* 331 */ )?((__ret_1060==2-1 /* 332 */ )?(0 /* 332 */ ):__ret_1060+1 /* 333 */  /* 333 */ ):__round_1059 /* 335 */  /* 334 */ ;
assign __index_1061 /* 337 */ = __round_1059 /* 337 */ ;
assign __index_1062 /* 339 */ = ((__round_1059+1)>=2 /* 340 */ )?(__round_1059+1-2 /* 341 */ ):__round_1059+1 /* 343 */  /* 342 */ ;
assign __cond_1064 /* 242 */ = 0==__index_1061 /* 242 */ ;
assign __cond_1065 /* 242 */ = 1==__index_1061 /* 242 */ ;
assign __valid_1063 /* 346 */ = ((({ 1{__cond_1064} }&((__mem_sel_1041 /* 312 */ ))) /* 244 */ )|({ 1{__cond_1065} }&((__mem_sel_1042 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_1067 /* 242 */ = 0==__index_1062 /* 242 */ ;
assign __cond_1068 /* 242 */ = 1==__index_1062 /* 242 */ ;
assign __valid_1066 /* 346 */ = ((({ 1{__cond_1067} }&((__mem_sel_1041 /* 312 */ ))) /* 244 */ )|({ 1{__cond_1068} }&((__mem_sel_1042 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __ret_1060 /* 349 */ = (__valid_1063 /* 215 */ )?(__index_1061 /* 216 */ ):(__valid_1066 /* 215 */ )?(__index_1062 /* 216 */ ):(2 /* 213 */ ) /* 218 */  /* 217 */  /* 217 */ ;
assign __mem_sel_idx_1043 /* 80 */ = (__ret_1060 /* 350 */ ) /* 80 */ ;
assign ___mem_sel_idx_dly_1044 /* 81 */ = __mem_sel_idx_1043 /* 81 */ ;
assign __mux2req_ready_1046 /* 89 */ = (__mem_sel_idx_1039==0 /* 215 */ )?((1'b1 /* 86 */ ) /* 216 */ ):(__mem_sel_idx_1043==0 /* 215 */ )?((1'b1 /* 86 */ ) /* 216 */ ):((0 /* 88 */ ) /* 213 */ ) /* 218 */  /* 217 */  /* 217 */ ;
assign __cond_1069 /* 242 */ = __mem_sel_idx_dly_1040==0 /* 242 */ ;
assign __cond_1070 /* 242 */ = __mem_sel_idx_dly_1044==0 /* 242 */ ;
assign mem_req__0__rdata /* 90 */ = ((({ 64{__cond_1069} }&((mem__0__rdata /* 87 */ ))) /* 244 */ )|({ 64{__cond_1070} }&((mem__1__rdata /* 87 */ ))) /* 246 */ ) /* 90 */ ;
assign ___mux2req_ready_dly_1045 /* 93 */ = __mux2req_ready_1046 /* 93 */ ;
assign mem_req__0__ready /* 94 */ = __mux2req_ready_1046 /* 94 */ ;
assign __cond_1072 /* 242 */ = (__mem_sel_idx_1039==0)&&__mem_sel_1037 /* 242 */ ;
assign __addr_t_1071 /* 111 */ = (({ 32{__cond_1072} }&(((mem_req__0__addr) /* 109 */ ))) /* 244 */ ) /* 111 */ ;
assign __mem_addr_t_1073 /* 112 */ = __addr_t_1071-0 /* 112 */ ;
assign mem__0__addr /* 113 */ = __mem_addr_t_1073[31:0] /* 113 */ ;
assign __cond_1074 /* 242 */ = (__mem_sel_idx_1039==0)&&__mem_sel_1037 /* 242 */ ;
assign mem__0__wdata /* 114 */ = (({ 64{__cond_1074} }&((mem_req__0__wdata /* 108 */ ))) /* 244 */ ) /* 114 */ ;
assign __cond_1075 /* 242 */ = (__mem_sel_idx_1039==0)&&__mem_sel_1037 /* 242 */ ;
assign mem__0__we_n /* 115 */ = (({ 1{__cond_1075} }&((mem_req__0__we_n /* 106 */ ))) /* 244 */ ) /* 115 */ ;
assign mem__0__ce_n /* 116 */ = ((__mem_sel_idx_1039==0)&&__mem_sel_1037 /* 215 */ )?(((!mem_req__0__valid) /* 107 */ ) /* 216 */ ):((1'b1 /* 110 */ ) /* 213 */ ) /* 218 */  /* 217 */ ;
assign __cond_1077 /* 242 */ = (__mem_sel_idx_1043==0)&&__mem_sel_1041 /* 242 */ ;
assign __addr_t_1076 /* 111 */ = (({ 32{__cond_1077} }&(((mem_req__0__addr) /* 109 */ ))) /* 244 */ ) /* 111 */ ;
assign __mem_addr_t_1078 /* 112 */ = __addr_t_1076-512 /* 112 */ ;
assign mem__1__addr /* 113 */ = __mem_addr_t_1078[31:0] /* 113 */ ;
assign __cond_1079 /* 242 */ = (__mem_sel_idx_1043==0)&&__mem_sel_1041 /* 242 */ ;
assign mem__1__wdata /* 114 */ = (({ 64{__cond_1079} }&((mem_req__0__wdata /* 108 */ ))) /* 244 */ ) /* 114 */ ;
assign __cond_1080 /* 242 */ = (__mem_sel_idx_1043==0)&&__mem_sel_1041 /* 242 */ ;
assign mem__1__we_n /* 115 */ = (({ 1{__cond_1080} }&((mem_req__0__we_n /* 106 */ ))) /* 244 */ ) /* 115 */ ;
assign mem__1__ce_n /* 116 */ = ((__mem_sel_idx_1043==0)&&__mem_sel_1041 /* 215 */ )?(((!mem_req__0__valid) /* 107 */ ) /* 216 */ ):((1'b1 /* 110 */ ) /* 213 */ ) /* 218 */  /* 217 */ ;
//cell instance
endmodule
